1. Field of the Invention
The present invention relates to a semiconductor storage apparatus, particularly to a semiconductor storage apparatus of a hierarchical bit line system comprising a main bit line and a sub bit line.
2. Description of the Related Art
In a semiconductor storage apparatus, in order to achieve high density formation and a reduction in capacitance of a word line, conventionally, there has been used an array constitution of a main/sub word line type dividing a word line into a main word line (referred to also as xe2x80x9cglobal word linexe2x80x9d) and a sub word line.
FIG. 14 is a block diagram showing an example of a constitution of a semiconductor storage apparatus having an array constitution of a main/sub word line type, showing a constitution of EEPROM (electrically erasable and programmable read only memory). In reference to FIG. 14, each of memory cell arrays 1 is provided with an array power supply circuit 4, an X sub decoder 9 and a Y switch 2 and a bit line (not illustrated) above the memory cell array is connected to a data bus via the Y switch and connected to a reading/writing circuit. The array power source circuit 4 is supplied with a control signal from an array power supply control circuit 5 in accordance with writing operation and erasing operation.
According to the semiconductor storage apparatus having the constitution shown by FIG. 14, a size of an X decoder can be reduced by constituting the X decoder by an X main decoder 8 and the X sub decoders 9. However, there is needed a wiring for supplying a main word line from the X main decoder 8 to the respective X sub decoders 9 by passing above the respective memory cell arrays. Further, when a bit line (not illustrated) in the memory cell array 1 constitutes a first wiring layer and the main word line (not illustrated) constitutes a second wiring layer, a hierarchical bit line structure cannot be realized so far as a wiring layer is not added further above the memory cell array and a wiring region is not provided at a peripheral region or the like. Therefore, a data bus region is provided and the bit line of the memory cell array is connected to the data bus 7 via the Y switch 2 to thereby supply read data to the reading/writing circuit 6 and write data from the reading/writing circuit 6. Further, there is constructed a constitution in which a power supply control line from the array power supply control circuit 5 is wired at a periphery of the memory cell array region and is connected to the array power supply circuit 4 of each of the memory cell arrays.
FIG. 15 is a block diagram showing a constitution of EEPROM having an array constitution of a main/sub bit line type and FIG. 16 is a diagram showing a detailed constitution thereof (refer to U.S. Pat. No. 5,126,808).
In reference to FIG. 15, each of the memory cell arrays 1 is provided with the Y switch 2, the array power supply circuit 4 and the X decoder 3 and the main bit line is connected to the reading/writing circuit 6 by passing above the respective memory cell arrays in the vertical direction of the drawing. In each of the memory cell arrays, a sub bit line commonly connected to a drain of a memory cell transistor is connected to the main bit line via the Y switch.
In reference to FIG. 16, according to an array 500, EEPROM cells (00,0) through (mn,k) are arranged by a number of (k+1) of columns 100-0 through 100-k and (m+1) (n+1) of rows 200-00 through 200-mn and at respective rows 200, word lines WL are connected to control gates of the EEPROM cells in the rows.
The array 500 is provided with a plurality of page selecting transistors (0,0) through (m,k). The page selecting transistors (0,0) through (m,k) are arranged at (m+1) rows 300-0 through 300-m and each of the rows is provided with (k+1) of the page selecting transistors. Drain/source of the page selecting transistor (i, j) (notation xe2x80x9cixe2x80x9d designates page and notation xe2x80x9cjxe2x80x9d designates column) is connected to a bit line BLj. For example, the drain/source of the page selecting transistor (0,0) in the column 100-0 is connected to the bit line BLO.
At the column 100-j of the page 400-j, the drain of the EEPROM cell is connected to the page bit line BLj and sources of the cells in the array 500 are commonly connected.
According to the constitution shown by FIG. 15, in comparison with the main/sub word line constitution shown by FIG. 14, although the data bus region can be reduced, there is needed a region of power supply lines and control signal lines leading to an array power supply circuit.
Further, as literatures concerning the hierarchical bit line system of the main/sub bit lines, there are disclosed technologies for making constant a resistance value with regard to discharge current regardless of a position of a memory cell to be read in ROM of the hierarchical bit line system in, for example, Japanese Unexamined Patent Publication No. 4-311900 and so on.
As described above, according to the constitution of the conventional semiconductor storage apparatus, it is necessary to provide wiring regions for the data bus from the memory cell arrays, the power source lines and the control signal lines leading to the array power supply circuit and so on at the periphery of the memory cell array and accordingly, there poses a problem in which the chip size is difficult to reduce.
For example, in respect of memory cell arrays of 512 words 1024 columns, when the main/sub bit lines are constructed by a 1:2 constitution (two sub bit lines per main bit line), a first wiring layer is wired with 1024 of the sub bit lines and a second wiring layer is wired with 512 of the main bit lines. Normally, the second wiring layer is provided with a wiring rate of about a half of that of the first wiring layer and accordingly, in this case, in the second wiring layer, the wiring region becomes full by only wiring the main bit lines and other control signals and the like need to provide at peripheries of the memory cell arrays or the like.
That is, arbitrary signal lines cannot be arranged above the memory cell arrays and a reduction in the chip area is hindered.
Therefore, the present invention has been carried out in view of the above-described problems and it is an object thereof to provide a semiconductor storage apparatus capable of reducing a chip area.
In order to achieve the above-described object, according to an aspect of the present invention, there is provided a semiconductor storage apparatus, wherein sub bit lines commonly connected with drains of a plurality of memory cell transistors are connected to main bit lines via a plurality of stages of switches.
More in details, according to another aspect of the present invention, there is provided a semiconductor storage apparatus wherein one main bit line is provided to a plurality of sub bit lines commonly connected with drains of a plurality of memory cell transistors, wherein the plurality of sub bit lines are connected to ends on one side of Y switches at a first stage, control terminals of which are respectively inputted with column selecting signals and wherein ends on other side of the Y switches at the first stage are commonly connected and connected to the main bit line via Y switches at a second stage, control terminals of which are inputted with column selecting signals. Further, the above-described object can be achieved also by other aspects of the present invention, described below.